View 97U870AHI_6616022.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

integrated circuit systems, inc. ics97u870 advance information 0817?07/07/03 block diagram 1.8v wide range frequency clock driver pin configuration 40-pin mlf recommended application: custom on-board memory / zero delay board fan out product description/features: ics universal input: supports multiple switching standards low skew, low jitter pll clock driver 1 to 10 differential clock distribution (sstl_18 outputs) feedback pins for input to output synchronization spread spectrum tolerant inputs switching characteristics: period jitter: 40ps half-period jitter: 60ps cycle - cycle jitter 40ps output - output skew: 40ps a b 123456 c d e f g h j k 52-ball bga advance information documents contain information on products in the formative or design phase development. characteristic data and other specific ations are design goals. ics reserves the right to change or discontinue these products without notice. third party brands and names are the property of their respective owners. clkt0 clkc0 clkt1 clkc1 clkt2 clkc2 clkt3 clkc3 clkt4 clkc4 clkt5 clkc5 clkt6 clkc6 clkt7 clkc7 clkt8 clkc8 clkt9 clkc9 fb_outt fb_outc av dd fb_int clk_int clk_inc fb_inc pll powerdown control and test logic oe ld* or oe pll bypass ld* ld*, os or o e os gnd 10k-100 k * the logic detect (ld) powers down the device when a logic low is applied to both clk_int and clk_inc. vddq clkc2 clkt2 clk_int clk_inc vddq agnd avdd vddq gnd clkc7 clkt7 vddq fb_int fb_inc fb_outc fb_outt vddq oe os clkt3 clkc3 clkc4 clkt4 vddq clkt9 clkc9 clkc8 clkt8 vddq clkc1 clkt1 clkt0 clkc0 vddq clkc5 clkt5 clkt6 clkc6 vddq 1 10 11 20 21 31 30 40 ics97u870 12345 6 a clkt1 clkt0 clkc0 clkc5 clkt5 clkt6 b clkc1 gnd gnd gnd gnd clkc6 c clkc2 gnd nb nb gnd clkc7 d clkt2 vddq vddq vddq os clkt7 e clk_int vddq nb nb vddq fb_int f clk_inc vddq nb nb oe fb_inc g agnd vddq vddq vddq vddq fb_outc h avdd gnd nb nb gnd fb_outt j clkt3 gnd gnd gnd gnd clkt8 k clkc3 clkc4 clkt4 clkt9 clkc9 clkc8
2 ics97u870 advance information 0817?07/07/03 pin descriptions l a n i m r e t e m a n n o i t p i r c s e d l a c i r t c e l e s c i t s i r e t c a r a h c d n g ad n u o r g g o l a n a d n u o r g v a d d r e w o p g o l a n a l a n i m o n v 8 . 1 t n i _ k l cr o t s i s e r n w o d l l u p ) m h o k 0 0 1 - k 0 1 ( a h t i w t u p n i k c o l c t u p n i l a i t n e r e f f i d c n i _ k l c r o t s i s e r n w o d l l u p ) m h o k 0 0 1 - k 0 1 ( a h t i w t u p n i k c o l c y r a t n e l p m o c t u p n i l a i t n e r e f f i d t n i _ b ft u p n i k c o l c k c a b d e e f t u p n i l a i t n e r e f f i d c n i _ b ft u p n i k c o l c k c a b d e e f y r a t n e m e l p m o c t u p n i l a i t n e r e f f i d t t u o _ b ft u p t u o k c o l c k c a b d e e f t u p t u o l a i t n e r e f f i d c t u o _ b ft u p t u o k c o l c k c a b d e e f y r a t n e m e l p m o c t u p t u o l a i t n e r e f f i d e o) s u o n o r h c n y s a ( e l b a n e t u p t u o t u p n i s o m c v l s ov r o d n g o t d e i t ( t c e l e s t u p t u o q d d )t u p n i s o m c v l d n gd n u o r g d n u o r g v q d d r e w o p t u p t u o d n a c i g o l l a n i m o n v 8 . 1 ] 9 : 0 [ t k l cs t u p t u o k c o l c s t u p t u o l a i t n e r e f f i d ] 9 : 0 [ c k l cs t u p t u o k c o l c y r a t n e m e l p m o c s t u p t u o l a i t n e r e f f i d b nl l a b o n the pll clock buffer, ics97u870 , is designed for a v ddq of 1.8 v, a av dd of 1.8 v and differential data input and output levels. package options include a plastic 52-ball vfbga and a 40-pin mlf. ics97u870 is a zero delay buffer that distributes a differential clock input pair (clk_int, clk_inc) to ten differential pair of clock outputs (clkt[0:9], clkc[0:9]) and one differential pair feedback clock outputs (fb_outt, fboutc). the clock outputs are controlled by the input clocks (clk_int, clk_inc), the feedback clocks (fb_int, fb_inc), the lvcmos program pins (oe, os) and the analog power input (avdd). when oe is low, the outputs (except fb_outt/ fb_outc) are disabled while the internal pll continues to maintain its locked-in frequency. os (output select) is a program pin that must be tied to gnd or v ddq . when os is high, oe will function as described above. when os is low, oe has no effect on clkt7/clkc7 (they are free running in addition to fb_outt/fb_outc). when av dd is grounded, the pll is turned off and bypassed for test purposes. when both clock signals (clk_int, clk_inc) are logic low, the device will enter a low power mode. an input logic detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform a low power state where all outputs, the feedback and the pll are off. when the inputs transition from both being logic low to being differential signals, the pll will be turned back on, the inputs and outputs will be enabled and the pll will obtain phase lock between the feedback clock pair (fb_int, fb_inc) and the input clock pair (clk_int, clk_inc) within the specified stabilization time t stab . the pll in ics97u870 clock driver uses the input clocks (clk_int, clk_inc) and the feedback clocks (fb_int, fb_inc) to provide high-performance, low-skew, low-jitter output differential clocks (clkt[0:9], clkc[0:9]). ics97u870 is also able to track spread spectrum clocking (ssc) for reduced emi. ics97u870 is characterized for operation from 0c to 70c.
3 ics97u870 advance information 0817?07/07/03 function table s t u p n is t u p t u o l l p d d v ae os ot n i _ k l ct n i _ k l ct k l cc k l ct t u o _ b fc t u o _ b f d n ghxl h l h l h f f o / d e s s a p y b d n ghxh l h l h l f f o / d e s s a p y b d n glhl h ) z ( l *) z ( l *lh f f o / d e s s a p y b d n gllh l , ) z ( l * 7 t k l c e v i t c a , ) z ( l * 7 c k l c e v i t c a h lf f o / d e s s a p y b ) m o n ( v 8 . 1lhlh ) z ( l *) z ( l *lh n o ) m o n ( v 8 . 1llhl , ) z ( l * 7 t k l c e v i t c a , ) z ( l * 7 c k l c e v i t c a hl n o ) m o n ( v 8 . 1hxlhlhlh n o ) m o n ( v 8 . 1hxhlhlhl n o ) m o n ( v 8 . 1xxll ) z ( l *) z ( l *) z ( l *) z ( l *f f o ) m o n ( v 8 . 1xxhh d e v r e s e r *l(z) means the outputs are disabled to a low stated meeting the i odl limit.
4 ics97u870 advance information 0817?07/07/03 absolute maximum ratings supply voltage (vddq & avdd) . . . . . . . . . -0.5v to 2.5v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.5v to v ddq + 0.5v ambient operating temperature . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . -65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters ta = 0 - 70c; supply voltage avddq, vddq = 1.8 v +/- 0.1v (unless otherwise stated) parameter symbol conditions min typ max units input high current (clk_int, clk_inc) i ih v i = v ddq or gnd 250 a input low current (oe, os, fb_int, fb_inc) i il v i = v ddq or gnd 10 a output disabled low current i odl oe = l, v odl = 100mv 100 a i dd1.8 c l = 0pf @ 270mhz 300 ma i ddld c l = 0pf 500 a input clamp voltage v ik v ddq = 1.7v iin = -18ma -1.2 v i oh = -100 av ddq - 0.2 v i oh = -9 ma 1.1 1.45 v i ol =100 a0.250.10v i ol =9 ma 0.6 v input capacitance 1 c in v i = gnd or v ddq 23pf output capacitance 1 c out v out = gnd or v ddq 23pf 1 guaranteed by design, not 100% tested in production. operating supply current high-level output voltage v oh low-level output voltage v ol
5 ics97u870 advance information 0817?07/07/03 notes: 1. unused inputs must be held high or low to prevent them from floating. 2. dc input signal voltage specifies the allowable dc execution of differential input. 3. differential inputs signal voltages specifies the differential voltage [vtr-vcp] required for switching, where vtr is the true input level and vcp is the complementary input level. 4. differential cross-point voltage is expected to track variations of v ddq and is the voltage at which the differential signal must be crossing. recommended operating condition ( see note1 ) t a = 0 - 70c; supply voltage avdd, vddq = 1.8 v +/- 0.1v (unless otherwise stated) parameter symbol conditions min typ max units supply voltage v ddq , a vd d 1.7 1.8 1.9 v clk_int, clk_inc, fb_inc, fb_int 0.35 x v ddq v oe, os 0.35 x v ddq v clk_int, clk_inc, fb_inc, fb_int 0.65 x v ddq v oe, os 0.65 x v ddq v dc input signal voltage (note 2) v in -0.3 v ddq + 0.3 v dc - clk_int, clk_inc, fb_inc, fb_int 0.3 v ddq + 0.4 v ac - clk_int, clk_inc, fb_inc, fb_int 0.6 v ddq + 0.4 v output differential cross- voltage (note 4) v ox v ddq /2 - 0.10 v ddq /2 + 0.10 v input differential cross- volta g e (note 4) v ix universal input mode 0.45 (v ih - v il )v dd /2 0.55 (v ih - v il )v high level output current i oh -9 ma low level output current i ol 9ma operating free-air temperature t a 070c v ddq - 0.4 v 0.8 v ddq + 0.3 v clk_int, clk_inc universal input mode clk_int, clk_inc universal input mode 0.4 differential input signal voltage (note 3) v id low level input voltage v il high level input voltage v ih low level universal input volta g e v il high level universal input voltage v ih
6 ics97u870 advance information 0817?07/07/03 notes: 1. switching characteristics guaranteed for application frequency range. 2. static phase offset shifted by design. timing requirements t a = 0 - 70c supply voltage avdd, vddq = 1.8 v +/- 0.1v (unless otherwise stated) parameter symbol conditions min max units max clock frequency freq op 1.8v+ 0.1v @ 25c 95 370 mhz application frequency range freq app 1.8v+ 0.1v @ 25c 160 350 mhz input clock duty cycle d tin 40 60 % clk stabilization t stab 15 s switching characteristics 1 t a = 0 - 70c supply voltage avdd, vddq = 1.8 v +/- 0.1v (unless otherwise stated) parameter symbol condition min typ max units output enable time t en oe to any output 4.73 8 ns output disable time t dis oe to any output 5.82 8 ns period jitter t j it (p er ) -30 30 ps half-period jitter t j it ( h p er ) -60 60 ps input clock 1 2.5 4 v/ns output enable (oe), (os) 0.5 v/ns output clock slew rate slr1 ( o ) 1.5 2.5 3 v/ns t j it ( cc+ ) 040ps t j it ( cc- ) 0 -40 ps dynamic phase offset t ( ) d y n -20 20 ps static phase offset t spo 2 -50 0 50 ps output to output skew t ske w 40 ps ssc modulation frequency 30.00 33 khz ssc clock input frequency deviation 0.00 -0.50 % pll loop bandwidth (-3 db from unity gain) 2.0 mhz cycle-to-cycle period jitter input slew rate slr1(i)
7 ics97u870 advance information 0817?07/07/03 gnd ics97u870 v dd v (clkc) v (clkc) scope c=10p f -vdd/2 gnd - gnd vdd/2 z=6 z = 2.97" z = 120 ? z = 2.97" 0 ? z=60 ? z=50 ? z=50 ? r=10 ? r=10 ? v (tt) v (tt) c=10pf note: v tt = gnd t c(n) t c(n+1) t jit(cc) =t c(n) t c(n+1) figure 1. ibis model output load figure 2. output load test circuit y , fb_outc x y , fb_outt x parameter measurement information ics97u870 figure 3. cycle-to-cycle jitter r = 1m ? c = 1 pf r = 1m ? c = 1 pf
8 ics97u870 advance information 0817?07/07/03 (n is a large number of samples) t ( ) n+1 t ()n t () = 1 n= n t ()n n clk_inc clk_int fb_inc fb_int t (skew) y # x y , fb_outc x y , fb_outt x y , fb_outc x y , fb_outt x y , fb_outc x y , fb_outt x y x parameter measurement information figure 4. static phase offset figure 5. output skew 1 f o t = t - (jit_per) t c(n) c(n) 1 f o figure 6. period jitter
9 ics97u870 advance information 0817?07/07/03 clock inputs and outputs 80% 20% 80% 20% t slr t slf v id ,v od figure 8. input and output slew rates parameter measurement information t jit(hper_n) t jit(hper_n+1) 1 f o y , fb_outc x y , fb_outt x figure 7. half-period jitter t jit(hper) t jit(hper_n) 1 2xf o =-
10 ics97u870 advance information 0817?07/07/03 figure 9. dynamic phase offset figure 10. time delay between oe and clock output (y, y) t ( ) t ( ) fbin fbi n ck ck t ( )dyn t ( )dyn t ( )dyn t ( )dyn ssc of f ssc on ssc on ssc off 5 0 % vddq t en t dis oe oe y/ y y 50 % vddq y y y 5 0 % vddq 50 % vd dq
11 ics97u870 advance information 0817?07/07/03 figure 11. av dd filtering - place the 2200pf capacitor close to the pll. - use a wide trace for the pll analog power & ground. connect pll & caps to agnd trace & connect trace to one gnd via (farthest from pll). - recommended bead: fair-rite p/n 2506036017y0 or equivalent (0.8 ohm dc max, 600 ohms @ 100 mhz).
12 ics97u870 advance information 0817?07/07/03 ordering information ics97u870 y ht designation for tape and reel packaging package type h = bga revision designator (will not correlate with datasheet revision) device type prefix ics = standard device example: ics xxxx y h - t symbol min. nom. max. a 0.86 0.93 1.00 a1 0.15 0.18 0.21 a2 0.71 0.75 0.79 d 4.40 4.50 4.60 e 6.90 7.00 7.10 i j m aaa 0.10 bbb 0.10 ccc 0.10 b 0.35 0.40 0.45 e 0.625 ref. 0.575 ref. 6x10 0.65 typ. 0.15 min. 0.40 dia. 0.15 typ. 1.00 max. 3 2 1 a b c d e f g h i j seating plane a1 top view e d
13 ics97u870 advance information 0817?07/07/03 ordering information ics97u870 ykt example: 40-pin mlf l o b m y ss n o i s n e m i d n o m m o c a- 5 8 . 00 9 . 0 1 a0 0 . 01 0 . 05 0 . 0 2 a- 5 6 . 00 8 . 0 3 af e r 0 2 . 0 dc s b 0 0 . 6 1 dc s b 5 7 . 5 ec s b 0 0 . 6 1 ec s b 5 7 . 5 q2 1 p4 2 . 02 4 . 00 6 . 0 r3 1 . 07 1 . 03 2 . 0 d n o i t a r a v h c t i p ec s b 0 5 . 0 n0 4 d n0 1 e n0 1 l0 3 . 00 4 . 00 5 . 0 b8 1 . 03 2 . 00 3 . 0 q0 0 . 00 2 . 05 4 . 0 2 d5 7 . 20 9 . 25 0 . 3 2 e5 7 . 20 9 . 25 0 . 3 designation for tape and reel packaging package type k = mlf revision designator (will not correlate with datasheet revision) device type prefix ics = standard device ics xxxx y k - t
g l o b a l s i t e s a ? a ? a ? a ? a ? a ? a ? g l o b a l s i t e s a ? a ? a ? a ? a ? a ? a ? ? ? ? e m a i l ? | ? p r i n t s e a r c h e n t i r e s i t e s e a r c h e n t i r e s i t e c o n t a c t i d t ? | ? i n v e s t o r s ? | ? p r e s s d o c u m e n t s e a r c h ? | ? p a c k a g e s e a r c h ? | ? p a r a m e t r i c s e a r c h ? | ? c r o s s r e f e r e n c e s e a r c h ? | ? g r e e n & r o h s ? | ? c a l c u l a t o r s ? | ? t h e r m a l d a t a ? | ? r e l i a b i l i t y & q u a l i t y ? | ? m i l i t a r y ? 9 7 u 8 7 0 a ( d d r 2 p l l ) d e s c r i p t i o n 1 . 8 v w i d e r a n g e f r e q u e n c y c l o c k d r i v e r m a r k e t g r o u p d i m m a d d i t i o n a l i n f o a d d t o m y i d t ? [ ? ] h o m e > p r o d u c t s > m e m o r y i n t e r f a c e p r o d u c t s > r d i m m > d d r 2 > d d r 2 p l l > 9 7 u 8 7 0 a y o u m a y a l s o l i k e . . . 2 ? ? 1 ? ? r e l a t e d o r d e r a b l e p a r t s
a t t r i b u t e s 9 7 u 8 7 0 a h 9 7 u 8 7 0 a h i 9 7 u 8 7 0 a h i t 9 7 u 8 7 0 a h t 9 7 u 8 7 0 a k 9 7 u 8 7 0 a k i p a c k a g e c v b g a 5 2 ( b v 5 2 ) ? c v b g a 5 2 ( b v 5 2 ) ? c v b g a 5 2 ( b v 5 2 ) ? c v b g a 5 2 ( b v 5 2 ) ? v f q f p n 4 0 ( n l 4 0 ) ? v f q f p n 4 0 ( n l 4 0 ) ? s p e e d n a ? n a ? n a ? n a ? n a ? n a ? t e m p e r a t u r e c ? i ? i ? c ? c ? i ? v o l t a g e 1 . 8 v ? 1 . 8 v ? 1 . 8 v ? 1 . 8 v ? 1 . 8 v ? 1 . 8 v ? s t a t u s a c t i v e ? a c t i v e ? a c t i v e ? a c t i v e ? a c t i v e ? a c t i v e ? s a m p l e n o ? n o ? n o ? n o ? n o ? n o ? m i n i m u m o r d e r q u a n t i t y 3 2 5 ? 3 2 5 ? 2 5 0 0 ? 2 5 0 0 ? 1 9 6 0 ? 9 8 0 ? f a c t o r y o r d e r i n c r e m e n t 3 2 5 ? 3 2 5 ? 2 5 0 0 ? 2 5 0 0 ? 4 9 0 ? 4 9 0 ? 2 ? ? 1 ? ? t y p e t i t l e s i z e r e v i s i o n d a t e d a t a s h e e t ? 9 7 u 8 7 0 d a t a s h e e t 1 9 6 k b 0 4 / 0 6 / 2 0 0 6 p r o d u c t c h a n g e n o t i c e ? p c n # : t b - 0 6 0 5 - 0 5 n e w s h i p p i n g t r a y f o r c v b g a 5 2 l & 5 6 l 1 1 3 4 k b 0 6 / 2 9 / 2 0 0 6 ? p c n # : a - 0 6 0 7 - 0 2 i d t p e n a n g a s a l t e r n a t e a s s e m b l y f a c i l i t y f o r i c s c v b g a a n d f p b g a 1 0 0 k b 0 7 / 2 7 / 2 0 0 6 ? p c n # a - 0 6 0 7 - 0 5 g r e e n m o l d c o m p o u n d k m c 3 5 8 0 f o r b g a 1 9 5 k b 0 8 / 3 0 / 2 0 0 6 ? p c n # : a - 0 6 1 0 - 0 2 a s a t c h i n a a s a l t e r n a t e f a c i l i t y f o r c a b g a / c v b g a / f p b g a / t q f p / p q f p 2 5 3 k b 1 0 / 1 9 / 2 0 0 6 r e l a t e d d o c u m e n t s h o m e ? | ? s i t e m a p ? | ? a b o u t i d t ? | ? p r e s s r o o m ? | ? i n v e s t o r r e l a t i o n s ? | ? t r a d e m a r k ? | ? p r i v a c y p o l i c y ? | ? c a r e e r s ? | ? r e g i s t e r ? | ? c o n t a c t u s ? u s e o f t h i s w e b s i t e s i g n i f i e s y o u r a g r e e m e n t t o t h e a c c e p t a b l e u s e a n d p r i v a c y p o l i c y . c o p y r i g h t 1 9 9 7 - 2 0 0 7 i n t e g r a t e d d e v i c e t e c h n o l o g y , i n c . a l l r i g h t s r e s e r v e d . n o d e : w w w . i d t . c o m

▲Up To Search▲

Price & Availability of 97U870AHI

	To Download 97U870AHI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .